The Next Big Innovation in Microprocessors: Anant Agarwal (Part 6)
Check other articles in the series...Anant identified five significant areas where innovation had to occur for multicore processors to really take off. He addressed each of these areas. Here we discuss the interconnect bottleneck issues in further depth.
SM: So you are doing some set of pre-routing on a switch. AA: Exactly. Now that you have a switch on each tile, what you do is take these tiles and you lay them out on a chip in a checkerboard fashion.
SM: What is the basis of the routing algorithm? AA: Switches talk to each other and route packets around, which was part of the research. It is called dimensional routing, which is how you route packets from one point to the other. You route in one direction first, and then you change to the next direction. There are other routing algorithms, and they differ in efficiency and ease of implementation, but the basic idea is that they can shift packets around.
SM: All of this is invisible to the programmer? AA: It is completely invisible. As far as the programmer is concerned they could think of it as a big switch which is a magical bus that instantly transports packets around.
SM: This mesh interconnect is the first innovation? AA: Yes, because the bus was the existing bottleneck, we replaced it with mesh and removed the bottleneck. Our technology is called Intelligent Mesh, or iMesh. Tiled multicore is a way of taking these tiles and scaling up. The way you tile these things in a mesh, you can build chips with large cores; this means we are going to get thousand core chips by 2014. A lot of people believe the number of cores will become the new megahertz. The nice thing about this architecture is that it gives you computing by the yard. You can build chips based on the type of computing that you want. With an architecture based on tiles, it is like a fabric and you can cut as much as you want.
This segment is part 6 in a 15 part series Segment 7 →
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