The Next Big Innovation in Microprocessors: Anant Agarwal (Part 8)
Check other articles in the series...SM: The market you are pursuing is embedded processors, so you do not really have demand for the fatter operating systems, such as Windows Vista. AA: Right, that is not where we are, but if for some reason that became important to a customer it would be done. Each processor core is full featured, so they can run any operating system. We took off the shelf Linux and made our chip work with it because we did not want to build an operating system from scratch.
SM: You mentioned cache issues earlier, did you make any advances in cache structures? AA: That is the area of our third major innovation, which is a distributed coherent cache. Of all the challenges of multicore design, cache issues are one of the biggest. When you have multicore architecture, you can create a big L3 cache; in essence combine L1 and L2, and create a big giant cache.
The problem is big giant structures are low performance and high power. So we invented this technology called distributed coherent cache where you take this big giant cache, break it up into pieces, and put a piece of it on every tile. What we are able to do is inspect our local cache, and if you get what you want, we are done. If you don’t get what you want, we can treat the aggregate of all the other caches on the chip as a gigantic L3 cache.
One way to look at it is like a desk, the desk being our cache. Just imagine a technology where if you look on your desk, and you do not find a book, but you know the book is on someone else’s desk, and you can automatically fetch that from their desk.
SM: How do you find which desk it is on? AA: That is part of the technology, and it turns out that every piece of data has a home location. You know if it is not on your desk you can go check a specific desk, and you will find the book. There is a technology built in which allows for things to be located this way. It is a pretty simple algorithm. In this way I can treat the aggregate of all the other caches as my own L3 cache.
This segment is part 8 in a 15 part series Segment 9 →
Jump to part: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
