Tackling EDA’s Broken Business Model: Blaze DFM CEO Jacob Jacobsson (Part 5)
Check other articles in the series...SM: How are you charging for your software? Are you competing for EDA dollars?
JJ: We recently made an announcement with TSMC, and I think this is the way we will continue to do business. TSMC offers our software as a service. What they do is they offer a process node that is software enhanced by Blaze. If a customer chooses that, a mandatory software step will need to be run. We perform that software step. Customer gets this enhanced process and pays a premium for it. We participate in the process for that premium.
SM: What kind of numbers are we talking, range-wise?
JJ: It is far more than what an EDA company in the similar space would get.
SM: It sounds like it. I am deriving on the back of the envelope. $30B a years lost, if you can even pick up a percentage of that …
JJ: That is the right way of looking at it. I have to give a couple of caveats. Not all parametric loss is due to power, but it is by far the biggest source.
SM: What percentage is due to parametric loss?
JJ: About half.
SM: So about $15 billion of the market value loss.
JJ: That’s right. There are certain chips you can’t touch, like memory chips. It is still a big TAM, in the billions. We sit in the interface between design and manufacturing. When seen from a designer’s point of view we are a part of manufacturing, and when seen from a manufacturer’s point of view we are part of design. We will, over time, put more into this interface.
SM: That is exactly what I was going to say. You can tackle more pieces of the equation than simply parametric yield.
JJ: The vision here is that whatever the total TAM is, each one of these solutions would fill up more and more of it, until we have covered the entire TAM.
SM: What does the technology do?
JJ: We have knowledge of the design. We know the timing of the design. We look at the entire network of the design and which transistors are not timing critical. For those transistors we will change the gate length. For a 90 nanometer process a nominal transistor is 90 nanometers and we will change it to 94. The effect is that the transistor will consume less power, but it will also be slower so you need to know the timing. Each transistor contributes relatively little, but if you do this over the millions in the network the impact is 20-30%.
What you have done is you now have used your design knowledge. What we need from the foundry is for them to tell us how much they feel comfortable with changing this gate length. We use the allowance we get from the foundry to optimize as much as possible. You can’t do this as a design only tool because you need to have this allowance from the foundry, and you can’t do it as a manufacturing tool because you need to know design. You can only do it sitting between the two.
SM: Who came up with this technology?
JJ: One of our founders, Professor Andrew Kahng.
SM: It is quite brilliant!
JJ: It is deceptively brilliant. Understanding the idea takes only a couple of seconds. The difficulty is converting it into a business model. To do so successfully you need a powerful optimizer that has very good timing analysis. When I looked at the concept I really had to convince myself that from a designer’s point of view it would look enough like manufacturing that you could say you were a part of manufacturing and whatever improvement in chip pricing you get, the designer is not going to pay for it. We take the money on the manufacturing side.
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Don’t you have your numbers crossed? You should be extending (not shortening) the gate length to get less leakage:
“we will change the gate length. For a 99 nanometer process a nominal transistor is 99 nanometers and we will change it to 96. The effect is that the transistor will consume less power, but it will also be slower”
Hi Ms Mitra,
Quite an interesting series and certainly talks about changing the rules of the game. You are talking of volumes to drive home the profits. Given the existing state of the EDA market, I do not think this will work (you mentioned the EDA sales guys acting like commodity service earlier, which is true). Industry’s still stuck at < $5B. Maybe for new tools yes but for existing ones — do you really think this can be done unless all the vendors act like a cartel thereby forcing the design houses to pay per chip (which in turn would spark off regulatory action)?
I would appreciate your comments if you think this could be done for existing tools. For new tools, yes, this is probably the way going forward unless acquired.
Regards,
Arpan
It will be much harder within the current framework.
John - your observation is correct.