If you are considering becoming a 1M/1M premium member and would like to join our mailing list to receive ongoing information, please sign up here.

Subscribe to our Feed

DFM Vision

Posted on Monday, Jan 30th 2006

Many EDA startups got funded in the last 3 years to address Design For Manufacturability of Chips. Catena, however, was an internal Cadence project that finally sees light of day.

Catena does post-layout optimization on shape-based parameters (vias, wires) to arrive at a better interconnect design, before handing off to the Fab or the Foundry.

As chips gets denser and denser, the pressure on layout engines intensifies, to accomodate all this functionality within a tiny perimeter. The victim, naturally, is yield.

Hence, the chip industry has been looking for ways to handle yield issues at the design stage.

This step is one in the right direction.

However, it is still a long way from being able to do predictive modeling using parameters of the manufacturing process before and during layout. Setting constraints and catching violations or risks pre- and during layout are still more valuable than correcting things after, as the degrees of freedom tend to go down dramatically as the process progresses.

Catena, therefore, is only a tiny step in the direction of a massive and ambitious vision that many in the industry harbor. My articulation of this vision is as follows: An exhaustive Design Rule Checker (DRC) that contains in its heart an Expert System that understands the manufacturing Process and Equipments, Properties of Materials, Temperatures, Signal Integrity, Power and Voltage issues, etc. This uber-DRC will then run through its rule-base – every Layout decision, make estimates about downstream Layout options/decisions (like a Chess Player), and help along the Layout optimization process.

And a lot more!

Hacker News
() Comments

Featured Videos


Sramana, your take on the DFM vision is exactly what the chip designer needs. However, in order for the tool to be effective, it needs to understand the process variations and defects. That is the true value of the expert system. Any CS graduate student can churn out the expert system DRC, the value comes from knowledge that can be included.

Fabs are notoriously tight fisted with respect to this knowledge. They will NOT share this information unless its its an ATI or a Qualcomm, never with a small EDA startup that will seek to give this info out to the general public.

This is the problem that most of the DFM startups are running into. It is a pain-point but the business model and value chain needs to be ironed out. Since TSMC is starting to provide DFM qualifying services to their IP suppliers and customers, that could be a potential exit strategy for these DFM startups – being bought by a foundry.

Prasad Tuesday, January 31, 2006 at 4:07 PM PT


DFM at this level is not for startups. It’s something that requires Cadence+TSMC+KLA-Tencor joining hands.

Your reasoning is spot on!


Sramana Mitra Tuesday, January 31, 2006 at 5:54 PM PT

[…] And here are two pieces on two growth areas within EDA that are still receiving some funding: DFM Vision – Clearshape, Blaze, Aprio are working on this area. RTL Hand-off and Predictive Prototyping – Atrenta could crack this code. […]

Sramana Mitra on Strategy » Blog Archive » Future of EDA : Addendum Friday, October 27, 2006 at 1:58 PM PT

[…] recommend you catch up on some readings: In Mentor Graphics: Target for SilverLake?, Future of EDA, DFM Vision, RTL Hand-off and Predictive Prototyping, Future of EDA: Addendum, I discussed the future of the […]

Cadence Takes a Page Out of Microsoft’s PlayBook - Sramana Mitra on Strategy Tuesday, June 17, 2008 at 10:50 AM PT