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RTL Hand-off & Predictive Prototyping

Posted on Sunday, Feb 26th 2006

I don’t recall exactly when Gary Smith, Chief EDA Analyst at Gartner coined the phrase Silicon Virtual Prototyping (SVP). It has been a while.

Many EDA industry insiders believe accurate SVP and RTL Hand-off to be the holy grail in the increasingly complex and expensive IC Design process. The hypothesis is, if you can find errors, including architecture level issues with a design early on in the design cycle, you can fix them early too. Degrees of freedom are high in the early stages of design, whereas after Synthesis, and even more so after Layout, fixing fundamental design problems becomes exceedingly difficult and expensive.

Predicated upon this premise, Tommy Eng was one of the first to launch a company, Tera Systems. There have been other players like InTime and Atrenta, and several ASIC vendors embraced the notion of RTL Hand-off as the preferred means of receiving design specs, including IBM. Almost all the structured ASIC vendors also embraced the methodology, although at this point, the industry at large is still using Netlist Handoff, as the preferred methodology, not RTL Hand-off.

The approach for estimating very large chips that Tera came up with, was to create a high-level abstraction of functional building blocks (adders, multiplexers, etc.), analyze and optimize those blocks, establish the constraints, and then prototype the full chip by applying those constraints at that higher level of abstraction. All aspects of design can be put through the same treatment: Timing, Power, Signal Integrity, Testability, and Physical, the last being one of the toughest to estimate.

I had asked industry veteran Ron Rohrer, once: “Why is it so difficult to deliver an RTL prototyping solution?” Ron identified the key issue that has killed many attempts at solving the same problem. “Accuracy”, he replied.

Indeed, the moment you have to estimate a design, the accuracy of the estimate becomes a hairy issue.

There are still other brand new startups taking a crack at the same problem, and some are walking the funding circuits. It remains to be seen who else gets how far.

It is a difficult, important problem. One of the last few BIG opportunities remaining in EDA, around which, perhaps, a reasonably large $100 Million company can be built, because no matter what, the solution is so incredibly valuable, that customers WILL pay for it.

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Very well written analysis. So, why did Tera go out of business?

You would think that if they could estimate chip size and speed within the “ballpark”, it would be useful. Perhaps one of the reasons such tools haven’t taken off is that you may be able to push your tools through synthesis/floorplanning/placement in a reasonable time to get accurate estimates.

Is First Encounter considered an SVP tool? Not by your definition, though I think its been categorized thusly. It requires a netlist, but quickly lets you floorplan and place the design.

John Busco Friday, March 3, 2006 at 9:14 PM PT

As far as I know, Tera wasn’t able to execute on the engineering side. It’s a hard technical problem, and so far, no one I know has managed to deliver a solution.

And no, First Encounter, from the point-of-view of this problem, is not the solution.

Sramana Mitra Friday, March 3, 2006 at 9:48 PM PT

[…] And here are two pieces on two growth areas within EDA that are still receiving some funding: DFM Vision – Clearshape, Blaze, Aprio are working on this area. RTL Hand-off and Predictive Prototyping – Atrenta could crack this code. […]

Sramana Mitra on Strategy » Blog Archive » Future of EDA : Addendum Friday, October 27, 2006 at 1:58 PM PT

[…] I have written extensively about the structural dysfuctions of the EDA industry in Future of EDA, Future of EDA: Addendum. The only two growth areas in the EDA market are Design for Manufacturability / Yield (DFM / DFY) and the pre-synthesis part of the flow that includes system-level design, hardware-software codesign, and prototyping. […]

Sramana Mitra on Strategy » Blog Archive » Is Cadence Growing at the Expense of Magma? Sunday, February 18, 2007 at 4:20 PM PT

I had written a technical paper on RTL prototyping ,and conducted a technical meet.. when i work’d at Atrenta, Software R&D @ Noida/single AE(myself) developed the One Team Implement product(RTL prototype)
from scratch .

Ravi Vardarajan(a ex Tera and ex Cadence employee) and Atrenta Fellow said that Tera Systems, main problem was inaccuarte mapping of models , which were Tera custom and had huge complex logic models..leading to poor timing correlation. Tera went out of business.

The One Team Implement ,was capable of
handling flat designs..but hierarchical ones
had to be manually tweaked, which was a limitation that R&D didnt fix.

On Johns Q; i have had prior work exp
@ Cadence SPnR div, San jose..i worked with
First Encounter..with clients Cisco/cortina as a FAE on multimillion gate designs.

FE is good for only initial placement feasibility analysis..but for RTL prototype..crossprobing from actual Final Routing wires needs to be feedback to RTL block designer , for them to make RTL level code modifications,resulting in much higher System level abstraction.

–Vikas Kuchu
[ former employee @ Cadence & Atrenta Inc]

Vikas Kuchu Friday, February 22, 2008 at 1:53 AM PT

Reading this article is as if First Encounter never existed. I have been Silicon Virtual Prototyping(SVP) since the turn of the century (Early 2000’s) with good accuracy and predictability, that has steadily increase to today.

Will a SVP from FE predict every possibility, no but it will get you within 90 to 95% accuracy, depending on your clock tree latency and variation.

FYI… To all the RTL designers reading this Cadence, moved this level of accuracy into their Synthesis Compiler too. With RC Physical you can achieve these type of results in the VERY next step after RTL.

Cadence User Sunday, February 24, 2008 at 8:36 AM PT

Did First Encounter stop the drop in design starts?

Sramana Mitra Sunday, February 24, 2008 at 5:15 PM PT