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The Next Big Innovation in Microprocessors: Anant Agarwal (Part 9)

Posted on Tuesday, Aug 28th 2007

I am curious how Anant addresses the intellectual property strategy for Tilera. In the back of my mind is the story of Tessera, a company that has had fundamental innovations in chip scale packaging, and today every single manufacturer of miniaturized consumer devices violate their patent, and pay them royalties.

Some of the innovations that Anant is working with date back to the early-mid nineties. Thus, it is very likely that as these patents get issued, many other multicore efforts from other vendors, both startups and larger companies, would be infringing upon them. A well-thought through IP strategy is a must, given how much Tilera has to gain from it.

SM: Is your technology, in particular distributed cache, proprietary? AA: Yes, as a matter of fact we have a lot of IP filed. We have 40+ patents pending on many of these technologies. The benefit of this technology is that you get the speed of a small cache. Imagine having a Volkswagen bug – you get the speed and efficiency of a small car, but when you want the capacity to transport 10,000 people it is like you can magically harness 100 cars from your neighborhood automatically and it is like they are your cars and you can carry everyone.

SM: You are trading off the size, but increasing the capacity. AA: You get low latency and high capacity through this distributed cache.

SM: We have discussed three of the innovations, so that leaves us with two more. Which would you like to discuss next? AA: The fourth innovation is a multicore hardwall. The idea there is that if you look at servers, with multiple blades in a rack, where people run multiple operating systems on a single blade, there is a need to be able to protect their shared resources; the whole virtualization problem.

We built technology in our chip where we can run multiple applications under multiple operating systems. You can protect virtual spaces from each other on the same chip. It is called a multicore hardwall. Essentially we can erect a fence around a set of cores, and any message which attempts to cross that fence will be stopped. There is hardware in the mesh work to do that, so it is a key virtualization technology for multicore.

[To Be Continued]

[Part 8]
[Part 7]
[Part 6]
[Part 5]
[Part 4]
[Part 3]
[Part 2]
[Part 1]

This segment is part 9 in the series : The Next Big Innovation in Microprocessors: Anant Agarwal
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Great post! Very interesting, thanks

opensemi Tuesday, August 28, 2007 at 1:35 PM PT

Interesting comment !!

FPGA Design Thursday, April 17, 2008 at 11:30 AM PT