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Intel’s Multi-core Future

Posted on Thursday, Sep 13th 2007

Intel (NASDAQ: INTC) is the world’s largest semiconductor company. It shot into limelight riding the famous “Intel Inside” marketing and branding campaign in 1990. Today, with an employee strength of 90,300 Intel currently ranks 62nd in the Fortune 500 list on the back of FY/06 revenues of $35.38 billion. This is however down from its 49th rank (FY/05 revenues $38.8 billion) a year back.

Intel’s revenues are nearly 7 times that of its immediate rival AMD, and in the last quarter (Q2/07) it held an overwhelming 80.3% of market share against AMD’s 11%. Yet it is not uncommon to find the two sparring at each other over invention of new technologies in order to garner more market share.

Their latest fight for turf seems to be around the development of multi-core multiprocessors otherwise known as chip-level multiprocessor, CMP. As things now stand, Intel’s answer is the Teraflops Research Project (TRP) against AMD’s just-announced launch of the new Quad-core microprocessor code-named Barcelona. Clearly, the battle in microprocessors has moved to multi-core / CMP, and Intel and AMD are lining up ammunition to fight the ensuing battles of 8, 16, 32, 64, 128 cores over the next decade.

In TRP, Intel claims that it has developed the world’s first programmable processor that delivers supercomputer-like performance from a single, 80-core chip. TRP, however, is still a research project, and a commercial mainstream microprocessor such as the TRP with a power-efficient 80-core chip is still a long ways away from fruition.

The largest multi-core chip that is actually shipping today is Tilera’s 64-core TILE64™ family of CMP unveiled last month by the company. My interview with Tilera’s founder and CTO Anant Agarwal is here. However, Tilera is not going after the mainstream microprocessor market, but attacking the Intelligent Networking and Video Server markets via embedded processors.

With rapid expansion in PC and laptop sales internationally, and a whole new generation of computer users expected to enter the market over the next decade, there is good deal of excitement in the mainstream microprocessor markets. The high end of this market is looking for more performance, and that is where, multi-core / CMP looks to be the solution.

But why does CMP look so promising?

As Anant Agarwal explains, CMP takes the place of single-core processors that had become so complex with additions of more and more transistors that it reached a technological dead-end. All known mechanisms of extracting performance out of a single processor maxed out. Furthermore, designers hit the wall in dimensions such as Power and Wire Delays.

The architecture that CMP’s are exploring, as Anant reveals, is essentially a grid-like mesh network of processors each of which has a processor core and a switch. The mesh network eliminates the need for a common bus for communication between different cores, thus optimizing the interconnect delay factor and also optimizes power consumption. Both Tilera’s TILE64 and Intel’s Teraflops Research Chip follow the mesh architecture for these reasons.

The Tile64 contains its processors in an 8 by 8 grid with each one capable of between 600 and 900-MHz clock frequency while consuming between 170 and 300 milliwatts per core. Idle tiles can be put into low-power sleep mode. The TRP Research chip can go all the way up to 5.7 GHz, but it has to trade energy efficiency.

Conceivably, somewhere in the future, companies such as Intel, AMD, Tilera, and other challengers will continue to make greater strides in optimizing the performance-power trade-off based on the base mesh architecture for multi-core chips.

On July 16 Intel debuted the first-ever dual-core Core 2 Extreme X7800 processor for mobile and notebook PCs. Intel also launched desktops based on its Q6700 processor, which is its first quad-core technology. It intends offering its first quad-core chip for laptops in 2008. With the convergence device movement gaining momentum, Intel has to keep an eye on solving the power-performance problem aggressively, since that will continue to be the secret sauce that would help them gain ground in that segment.

The other big challenge for all these CMP chips is programmability. Tilera has created a way to port existing OS software to its chip, and later optimize performance. However, its work in the embedded domain is relatively less challenging than running a fat desktop or server OS like Windows Vista. That is the challenge awaiting Intel (and AMD), as it scales to the higher-core dimensions.

INTC has been steadfast in R&D spending. Between 2001 and 2005, it spent $22.1 billion, and this year FY-07 it expects to spend $5.7 billion on R&D making it one of highest spenders on this line item.

INTC has upped the Q3/07 revenue expectation to $9.4 billion to $9.8 billion against earlier prediction of $9 billion to $9.6 billion on the back of good sales of laptop computers. Its Q2/07 revenue of $8.7 billion shows 8% y-o-y growth but falls short by 2% from the previous quarter.

Similar trends are seen in case of operating income of $1.35 billion (+25% y-o-y; –19% versus Q1/07), net income of $1.3 billion (+44%; –22%) and per-share earnings of 22 cents (+47%; –21%).

Interestingly, INTC has remained largely range-bound over the past year. Since April, however, the stock price has been on an upward move after nearly testing the 52-week low. This month, it is trading in the $25-$26 range.

So what is the outlook for Intel?

I think, the answer will lie in what ground it breaks in the multicore arena, in terms of performance, power efficiency, and programmability, without infringing on Intellectual Property that belongs to others who are further along in this research domain. Massively Parallel Processing (MPP) is a domain of computer architecture that has been researched for almost 20 years now. Intel will need to avoid the land mines of prior art as it looks for its own unique solutions.

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