SiP versus Structured ASICs

Semiconductors and Electronics have invaded every aspect of our lives in fairly extensive ways. During the last quarter of the twentieth century, this segment received enormous attention, venture investment, and duly provided some amazing vision, thought leadership, and innovation.

Now, in the first decade of the 21st Century, the industry is showing signs of hitting the wall. Cost structures are out-of-whack, the need or desire to go to the next node down is no longer as burning after 90nm, and VCs find it difficult to extract value from their chip investments.

New design paradigms are emerging as a result.

This week, Vinod Khosla reinforced his stake in the ground by putting in an additional $7.5 Million into eASIC, targeting the market segment defined in between FPGA and Standard Cell and dubbed Structured ASIC. LSI Logic has been going after this space for a few years now with the RapidChip initiative, and it does not look like a runaway success so far – certainly not enough to deliver LSI out of its persistent miseries.

Now, Ronnie Vashista of RapidChip has become the head of marketing for eASIC. I am curious as to why Mr. Khosla believes eASIC will succeed where LSI (and all the others) have failed.

Other players to track in this space are Tabula, Cradle, Tensilica, as well as a bunch of internal initiatives at large IDMs including NEC and Toshiba. Lightspeed Semiconductor has also been around for a long time, attempting to address the opportunity, without seeing light at the end of the tunnel.

On the other hand, the design paradigm that LSI Logic has not looked at and absolutely should – is System-in-Package (SiP). LSI has a large library of Silicon Intellectual Property, which they also call SIP. So, Mr. Corrigan ought to think about SIP in SIP as his potential deliverance strategy.

My bet, if I had to choose a design paradigm, between Structured ASICs and SiPs, would certainly be the latter.