Smaller, Faster, Cheaper – (Part 3)

By Lance Glasser, Guest Author

[Part 2]

We are seeing the research and development needed to stay at the leading edge of the semiconductor business increase steadily over the last few years. This has driven a consolidation of R&D into fewer bleeding edge players. This same phenomenon has also resulted in increasing buying power for the semiconductor alliances.

We have seen that the factor of two advantage in speed and cost one traditionally achieved moving from node to the adjacent node is now diminished. Indeed, if this factor became smaller than one, Moore’s Law would stop. On top of this, the amount of analog circuitry on an integrated circuit is increasing, and analog circuits do not shrink the same way as digital.

These two factors mean that the advantage of careening from node to node is diminished and, therefore, not all semiconductor companies feel the same compulsion to shrink quickly as they once did. This is causing an increasing gap between our leading edge wafer fabs and the mainstream. Older model tools are lasting longer in production. Together with the rise of the consumer market formfactor, this is also forcing an increased use of system-in-package technology, where each part can be optimized for what the technology does best.

Process control is certainly getting more difficult for wafer fabs as the number of devices on a wafer explode and the criticality of dimensional control becomes more exquisite. This has led to an increase in single-wafer processing. No longer are fab factories pipelined systems with a single path from input to output. Instead we have a combinatoric ravel of paths where tolerance stack ups can happen on any unique route. This puts pressure on the customer to sample more. On top of this, in-wafer variations are as big, if not bigger, than wafer-to-wafer variations.

Another megatrend is the increasing importance of control (e.g., overlay and CD) in lithography. While the pitch of single-exposure lines and vias are determined by the wavelength of light (in air or in water as appropriate), the linewidth is determined by the tightness of process control. Nonlinearities, for instance with spacers and etching or with double exposure, can double the spatial frequency of the lithography process. Such tricks are needed to get down to the pitches required by the 22 nm node and below with 193 nm light, and will undoubtedly be used. It is ironic, but in some sense, the poorer are the available choices to accomplish a task, the more money is spent on it. Lithography is an increasing fraction of the semiconductor capital budget.

The semiconductor industry continues to claw their way down Moore’s Law and inexorably drive down costs through lithography, through device material and structure innovation, through design, through yield management, through improvements in cycle time and operational excellence, though WIP (work in process), capital, and materials spending control, and through more sophisticated and focused vendor management. All of these activities are core to their survival.

Link to original article.

This segment is part 3 in the series : Smaller, Faster, Cheaper -
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